Feature scaling in integrated circuits is an enabler of more capable electronic devices. Scaling to smaller features increases densities of functional units in a given form factor as well as increasing device processing speeds. Device scaling, however, is not without issue. For example, in non-volatile charge trap memory devices, both data retention and sensing becomes increasingly difficult as the devices are scaled. FIG. 1 illustrates a cross-sectional view of a conventional non-volatile charge trap memory device where an oxide-nitride-oxide (ONO) stack is used to store charge in a nitride layer having a high density of charge trap states, forming a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) transistor. In functional terms, the first “Semiconductor” refers to the channel region of the substrate, the first “Oxide” refers to the tunneling layer, “Nitride” refers to the charge trapping layer, the second “Oxide” refers to the blocking layer and the second “Semiconductor” refers to the gate layer. The charge stored in the nitride trapping layer enables a SONOS transistor to provide non-volatility memory (NVM).
Referring to FIG. 1, non-volatile charge trap memory device 100 includes a SONOS gate stack 104 including a conventional ONO portion 106 formed over a silicon substrate 102. Non-volatile charge trap memory device 100 further includes source and drain regions 110 on either side of SONOS gate stack 104 to define a channel region 112. SONOS gate stack 104 includes a poly-silicon gate layer 108 formed above and in contact with ONO portion 106. Poly-silicon gate layer 108 is electrically isolated from silicon substrate 102 by ONO portion 106. ONO portion 106 typically includes an oxide tunneling layer 106A, a nitride or oxynitride charge trapping layer 106B, and an oxide blocking layer 106C overlying charge trapping layer 106B.
One limitation of conventional SONOS transistors is the poor quality of oxide employed as the blocking layer 106C which can reduce transistor performance (e.g. retention) through mechanisms such as carrier back streaming. The oxide of the blocking layer 106C is typically a deposited oxide, such as a high temperature oxide (HTO) formed with batch processing equipment. Generally, the HTO deposition process involves providing a silicon source, such as SiH4, SiH2Cl2, or SiCl4 and an oxygen-containing gas, such as O2 or N2O in a deposition chamber at a pressure of from about 50 mT to about 1000 mT, for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650° C. to about 850° C. While these deposition processes have been sufficient for relatively thick blocking layers, the wafer-to-wafer thickness non-uniformity, high film roughness and low film quality of such processes limit device performance as a SONOS transistor is scaled and the thickness of the blocking layer 106C is reduced.